Ball Grid Array (BGA) technology is an advanced type of semiconductor packaging technology, which is characterized by the use of a substrate mounted with a semiconductor chip on a front side thereof and implanted with a grid array of solder balls on a back side thereof, wherein the solder balls serve as input/output (I/O) connections to bond and electrically connect the semiconductor package to an external printed circuit board (PCB). This arrangement allows relatively more I/O connections to be accommodated on the same unit area of a chip carrier such as the substrate to comply with the requirement of a highly integrated semiconductor chip.
In order to make good use of the intended performances of the semiconductor chip in the BGA semiconductor package that is electrically connected to the external PCB via the solder balls, the circuit design of the chip carrier or substrate should be divided for different functions such that power supply, grounding and signal transmission.
U.S. Pat. No. 5,581,122 discloses a substrate provided with conductive rings such as a ground ring and a power ring and signal fingers thereon. Referring to FIG. 1 of a semiconductor device 1, a ground ring 111, a power ring 112 and a plurality of signal fingers 113 are arranged around a chip mounting area 110 on an upper surface of a substrate 11. A semiconductor chip 12 having a plurality of ground pads 121, power pads 122 and signal pads 123 is mounted on the chip mounting area 110. A wire-bonding process is performed to form a plurality of ground wires 131, power wires 132 and signal wires 133. The ground wires 131 electrically connect the ground pads 121 of the chip 12 to the ground ring 111 of the substrate 11; the power wires 132 electrically connect the power pads 122 of the chip 12 to the power ring 112 of the substrate 11; and the signal wires 133 electrically connect the signal pads 123 of the chip 12 to the signal fingers 113 of the substrate 11. Then, an encapsulant (not shown) is formed and encapsulates the upper surface of the substrate. A plurality of solder balls (not shown) are mounted to a lower surface of the substrate and electrically connected to the ground ring 111, the power ring 112 or the signal fingers 113 via corresponding conductive traces (not shown) provided on the lower surface of the substrate. When the semiconductor device 1 is bonded and electrically connected to an external device by the solder balls, the electrical quality of the chip 12 can be sustained via the ground ring 111 and the power ring 112, and the chip 12 can transmit electric charges through the ground ring 111 and is supplied with power through the power ring 112 during operation. Other related prior arts include U.S. Pat. Nos. 5,686,699 and 5,801,440.
Furthermore, along with the development of electronic devices made more compact in size and more complicated in structure, semiconductor package structures have been developed toward a chip size scale. Therefore, how to arrange high-density circuits in gradually reduced space of an integrated circuit carrier becomes am important issue in the associated industry. Accordingly, the integrated circuit carrier is generally designed to shorten a pitch distance between the adjacent conductive rings such as ground ring and power ring and a spaced distance between the conductive rings and the signal fingers, such that surface area of the integrated circuit carrier would be less occupied to thereby provide more area for arranging high-density circuits and facilitate the size miniaturization of the semiconductor device.
Referring to FIG. 2, when the pitch distance between the adjacent conductive rings or the spaced distance between the conductive rings and the signal fingers are reduced to be less than about 200 μm, a solder mask 20 for covering surface circuits of an integrated circuit carrier 2 cannot be precisely applied between the conductive rings 21 due to fabrication limitations, thereby making the area between the conductive rings 21 on the integrated circuit carrier 2 exposed. Then, when a semiconductor chip 22 is mounted on the integrated circuit carrier 2 and electrically connected to the integrated circuit carrier 2 via a plurality of wires 23, the wires 23 connected to the conductive ring 21 located relatively more far from the chip 22 have larger length and loop height and usually traverse above the other conductive ring 21 located closer to the chip 22. These wires 23 may easily sag and come into contact with the exposed underlying conductive ring 21 not covered by the solder mask 20, thereby leading to short circuit between the sagging wires 23 and the contacted conductive ring 21 and affecting reliability of the fabrication processes.
Referring to FIG. 3, in accordance with the foregoing problems, U.S. Pat. No. 6,449,169 discloses a solder mask 30 being applied between adjacent conductive rings 31 such as ground ring and power ring to support any sagging wires 33 and prevent the conductive rings 31 from short circuit. However, as discussed above that due to size miniaturization of the semiconductor device, the pitch distance between the adjacent conductive rings is reduced as much as possible and is not sufficient to accommodate a solder mask. Also the solder mask cannot be reliably provided between the conductive rings due to fabrication limitations, such that the patent is not well practicable in reality.
Therefore, considering the size miniaturization of semiconductor devices, the problem to be solved here is to provide an integrated circuit carrier and a semiconductor device with the carrier, which can prevent wires from short circuit with conductive rings due to undesirable contact between the wires and the conductive rings and provide industrial practicability.